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fujitsu microelectronics data sheet copyright?2006-2008 fujitsu microelec tronics limited all rights reserved 2008.12 for the information for microcontrolle r supports, see the following web site. http://edevice.fujitsu.com/micom/en-support/ 8-bit proprietary microcontrollers cmos f 2 mc-8fx mb95100am series mb95108am/f104ams/f104ans/f104ajs/f106ams/f106ans/f106ajs/ mb95f108ams/f108ans/f108ajs/f104amw/f104anw/f104ajw/f106amw/ mb95f106anw/f106ajw/f108amw/f108anw/f108ajw/fv100d-103 description the mb95100am series is general-purpose, single-chip micr ocontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. note : f 2 mc is the abbreviation of fuji tsu flexible microcontroller. feature ? f 2 mc-8fx cpu core instruction set optimized for controllers ? multiplication and division instructions 16-bit arithmetic operations bit test branch instruction bit manipulation instructions etc. ? clock main clock main pll clock sub clock (for dual clock product) sub pll clock (for dual clock product) (continued) ds07-12614-3e
mb95100am series 2 ds07-12614-3e (continued) ? timer 8/16-bit compound timer 2 channels 16-bit reload timer 8/16-bit ppg 2 channels 16-bit ppg 2 channels timebase timer watch prescaler (for dual clock product) ? lin-uart full duplex double buffer clock asynchronous (uart) or clock synchronous (sio) serial data transfer capable ? uart/sio full duplex double buffer clock asynchronous (uart) or clock synchronous (sio) serial data transfer capable ? i 2 c built-in wake-up function ? external interrupt interrupt by edge detection (rising, falling, or both edges can be selected) can be used to recover from lo w-power consumption (standby) modes. ? 8/10-bit a/d converter 8-bit or 10-bit resolution can be selected ? low-power consumption (standby) mode stop mode sleep mode watch mode (for dual clock product) timebase timer mode ? i/o ports : the number of maximum ports ? single clock product : 54 ports ? dual clock product : 52 ports port configuration ? general-purpose i/o ports (n-ch open drain) : 6 ports ? general-purpose i/o ports (cmos) : single clock product : 48 ports dual clock product : 46 ports ? programmable input voltage levels of port automotive input level / cmos input level / hysteresis input level ? flash memory security function protects the content of flash memo ry (flash memory device only)
mb95100am series ds07-12614-3e 3 memory lineup flash ram mb95f104ams/f104ans/f104ajs 16k bytes 512 bytes mb95f104amw/f104anw/f104ajw mb95f106ams/f106ans/f106ajs 32k bytes 1k byte mb95f106amw/f106anw/f106ajw mb95f108ams/f108ans/f108ajs 60k bytes 2k bytes mb95f108amw/f108anw/f108ajw
mb95100am series 4 ds07-12614-3e product lineup (continued) part number parameter mb95 108am mb95f 104ams/ mb95f 106ams/ mb95f 108ams mb95f 104ans/ mb95f 106ans/ mb95f 108ans mb95f 104amw/ mb95f 106amw/ mb95f 108amw mb95f 104anw/ mb95f 106anw/ mb95f 108anw mb95f 104ajs/ mb95f 106ajs/ mb95f 108ajs mb95f 104ajw/ mb95f 106ajw/ mb95f 108ajw type mask rom product flash memory product rom capacity* 1 60 kbytes (max) ram capacity* 1 2 kbytes (max) reset output yes no option* 2 clock system selectable single/dual clock* 3 single clock dual clock single clock dual clock low voltage detection reset yes/no no yes no yes clock supervisor no yes cpu functions number of basic instructions : 136 instruction bit length : 8 bits instruction length : 1 to 3 bytes data bit length : 1, 8, and 16 bits minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 mhz) interrupt processing time : 0.6 s (at machine clock frequency 16.25 mhz) general-pur- pose i/o ports ? single clock product : 54 ports (n-ch open drain : 6 ports, cmos : 48 ports) ? dual clock product : 52 ports (n-ch open drain : 6 ports, cmos : 46 ports) programmable input voltage levels of port : automotive input level / cmos input level / hysteresis input level timebase timer interrupt cycle : 0.5 ms, 2.1 ms, 8. 2 ms, 32.8 ms (at main oscillation clock 4 mhz) watchdog timer reset generated cycle at main oscillation clock 10 mhz : min 105 ms at sub oscillation clock 32.768 khz (f or dual clock product) : min 250 ms wild register capable of replacing 3 bytes of rom data i 2 c master/slave sending and receiving bus error function and arbitration function detecting transmitting direction function start condition repeated generation and detection functions built-in wake-up function uart/sio data transfer capable in uart/sio full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate generator nrz type transfer format, error detected function lsb-first or msb-first can be selected. clock asynchronous (uart) or clock synchro nous (sio) serial data transfer capable peripheral functions
mb95100am series ds07-12614-3e 5 (continued) part number parameter mb95 108am mb95f 104ams/ mb95f 106ams/ mb95f 108ams mb95f 104ans/ mb95f 106ans/ mb95f 108ans mb95f 104amw/ mb95f 106amw/ mb95f 108amw mb95f 104anw/ mb95f 106anw/ mb95f 108anw mb95f 104ajs/ mb95f 106ajs/ mb95f 108ajs mb95f 104ajw/ mb95f 106ajw/ mb95f 108ajw lin-uart dedicated reload timer allowing a wide r ange of communication speeds to be set. full duplex double buffer clock asynchronous (uart) or clock synchr onous (sio) serial data transfer capa- ble lin functions available as the lin master or lin slave. 8/10-bit a/d converter (12 channels) 8-bit or 10-bit resolution can be selected. 16-bit reload timer two clock modes and two counter operati ng modes can be selected. square wave- form output count clock : 7 internal clocks and external clock can be selected. counter operating mode : reload m ode or one-shot mode can be selected. 8/16-bit compound timer (2 channels) each channel of the timer c an be used as ?8-bit timer 2 channels? or ?16-bit timer 1 channel?. built-in timer function, pwc function, pw m function, capture function, and square waveform output count clock : 7 internal clocks and external clock can be selected 16-bit ppg (2 channels) pwm mode or one-shot mode can be selected. counter operating clock : 8 selectable clock sources support for external trigger start 8/16-bit ppg (2 channels) each channel of the ppg can be used as ? 8-bit ppg 2 channels ? or ? 16-bit ppg 1 channel ? . counter operating clock : eight selectable clock sources watch counter (for dual clock product) count clock : 4 selectable clock sour ces (125 ms, 250 ms, 500 ms, or 1 s) counter value can be set from 0 to 63. (capable of counting for 1 minute when selecting clock source 1 second and setting counter value to 60) watch prescaler (for dual clock product) 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) external interrupt (12 channels) interrupt by edge detection (rising, falling, or both edges can be selected.) can be used to recove r from standby modes. flash memory supports automatic programming, embedded algorithm write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of write/erase cycles (minimum) : 10000 times data retention time : 20 years erase can be performed on each block block protection with external programming voltage flash security feature for protec ting the content of the flash (mb95f108ams/f108ans/f108ajs/f 108amw/f108anw/f108ajw only) standby mode sleep, stop, watch (for dual clock product) , and timebase timer peripheral functions
mb95100am series 6 ds07-12614-3e (continued) *1 : for rom capacity and ram capacity, refer to ? memory lineup?. *2 : for details of option, refer to ? mask option?. *3 : specify clock mode when ordering mask rom. note : part number of the evaluation product in mb95 100am series is mb95fv100d- 103. when using it, the mcu board (mb2146-303a) is required.
mb95100am series ds07-12614-3e 7 oscillation stabilization wait time the initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. the maximum value is shown as follows. packages and corresponding products : available : unavailable oscillation stabilization wait time remarks (2 14 -2) /f ch approx. 4.10 ms (at main oscillation clock 4 mhz) mb95108am mb95f104ams/f104ans/ f104ajs mb95f106ams/f106ans/ f106ajs mb95f108ams/f108ans/ f108ajs mb95f104amw/f104anw/ f104ajw mb95f106amw/f106anw/ f106ajw mb95f108amw/f108anw/ f108ajw mb95fv100d-103 fpt-64p-m03 fpt-64p-m09 bga-224p- m08 part number parameter
mb95100am series 8 ds07-12614-3e differences among products and notes on selecting products ? notes on using evaluation products the evaluation product has not only the functions of t he mb95100am series but also those of other products to support software development for multiple series and models of the f 2 mc-8fx family. the i/o addresses for peripheral resources not used by the mb95100am series are therefore access-barred. read/write access to these access-barred addresses may cause peripheral re sources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. particularly, do not use word access to odd numbered by te address in the prohibited areas (if these access are used, the address may be read or write unexpectedly) . also, as the read values of prohibited addresses on th e evaluation product are different to the values on the flash memory and mask rom products, do not use these values in the program. the evaluation product do not support the functions of some bits in single-by te registers. read/write access to these bits does not cause hardware malfunctions. since the evaluation, flash memory, and mask rom products are designed to behave completely the same way in terms of hardware and software. ? difference of memory spaces if the amount of memory on the evaluation product is di fferent from that of the flash memory or mask rom product, carefully check the differ ence in the amount of memory from the model to be actually used when developing software. for details of memory space, refer to ? cpu core?. ? current consumption the current consumption of flash memory product is typically greater than for mask rom product. for details of current consumption, refer to ? electrical characteristics?. ? package for details of information on each package, refer to ? packages and corresponding products? and ? package dimensions?. ? operating voltage the operating voltage are different among the ev aluation, flash memory, and mask rom products. for details of operating voltage, refer to ? electrical characteristics?. ? difference between rst and mod pins the rst and mod pins are hysteresis in puts on the mask rom product. a pu ll-down resistor is provided for the mod pin of the mask rom product.
mb95100am series ds07-12614-3e 9 pin assignment (top view) (fpt-64p-m03, fpt-64p-m09) avss p30/an00 p31/an01 p32/an02 p33/an03 p34/an04 p35/an05 p36/an06 p37/an07 p40/an08 p41/an09 p42/an10 p43/an11 p67/sin p66/sot p65/sck 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avcc 1 48 p64/ec1 avr 2 47 p63/to11 pe3/int13 3 46 p62/to10 pe2/int12 4 45 p61/ppg11 pe1/int11 5 44 p60/ppg10 pe0/int10 6 43 p53/trg1 p83 7 42 p52/ppg1 p82 8 41 p51/sda0 p81 9 40 p50/scl0 p80 10 39 p24/ec0 p71/ti0 11 38 p23/to01 p70/to0 12 37 p22/to00 mod 13 36 p21/ppg01 x0 14 35 p20/ppg00 x1 15 34 p14/ppg0 vss 16 33 p13/trg0/adtg 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vcc c pg2/x1a ? pg1/x0a ? rst p00/int00 p01/int01 p02/int02 p03/int03 p04/int04 p05/int05 p06/int06 p07/int07 p10/ui0 p11/uo0 p12/uck0 64 * : single clock product is general-purpose port, and dual clock product is sub clock oscillation pin.
mb95100am series 10 ds07-12614-3e pin description (continued) pin no. pin name i/o circuit type* function 1avcc ? a/d converter power supply pin 2avr ? a/d converter reference input pin 3pe3/int13 p general-purpose i/o port. the pins are shared with the external interrupt input. 4pe2/int12 5pe1/int11 6pe0/int10 7p83 o general-purpose i/o port 8p82 9p81 10 p80 11 p71/ti0 h general-purpose i/o port. the pin is shared with 16-bi t reload timer ch.0 input. 12 p70/to0 general-purpose i/o port. the pin is shared with 16-bi t reload timer ch.0 output. 13 mod b an operating mode designation pin 14 x0 a main clock input oscillation pin 15 x1 main clock input/output oscillation pin 16 vss ? power supply pin (gnd) 17 vcc ? power supply pin 18 c ? capacitor connection pin 19 pg2/x1a h/a single clock product is general-purpose port (pg2) . dual clock product is sub clock i nput/output oscillation pin (32 khz). 20 pg1/x0a single clock product is general-purpose port (pg1) . dual clock product is sub clock input oscillation pin (32 khz). 21 rst b? reset pin 22 p00/int00 c general-purpose i/o port. the pins are shared with external interrupt input. large current port. 23 p01/int01 24 p02/int02 25 p03/int03 26 p04/int04 27 p05/int05 28 p06/int06 29 p07/int07 30 p10/ui0 g general-purpose i/o port. the pin is shared with uart/sio ch.0 data input.
mb95100am series ds07-12614-3e 11 (continued) pin no. pin name i/o circuit type* function 31 p11/uo0 h general-purpose i/o port. the pin is shared with uart/sio ch.0 data output. 32 p12/uck0 general-purpose i/o port. the pin is shared with uart/sio ch.0 clock i/o. 33 p13/trg0/ adtg general-purpose i/o port. the pin is shared with 16-bit ppg ch.0 trigger input (trg0) and a/d trigger input (adtg). 34 p14/ppg0 general-purpose i/o port. the pin is shared with 16-bit ppg ch.0 output. 35 p20/ppg00 h general-purpose i/o port. the pins are shared with 8/16-bit ppg ch.0 output. 36 p21/ppg01 37 p22/to00 general-purpose i/o port. the pins are shared with 8/16-bit compound timer ch.0 output. 38 p23/to01 39 p24/ec0 general-purpose i/o port. the pin is shared with 8/16-bit compound timer ch.0 clock input. 40 p50/scl0 i general-purpose i/o port. the pin is shared with i 2 c ch.0 clock i/o. 41 p51/sda0 general-purpose i/o port. the pin is shared with i 2 c ch.0 data i/o. 42 p52/ppg1 h general-purpose i/o port. the pin is shared with 16-bit ppg ch.1 output. 43 p53/trg1 general-purpose i/o port. the pin is shared with 16-b it ppg ch.1 trigger input. 44 p60/ppg10 k general-purpose i/o port. the pins are shared with 8/16-bit ppg ch.1 output. 45 p61/ppg11 46 p62/to10 general-purpose i/o port. the pins are shared with 8/16-bit compound timer ch.1 output. 47 p63/to11 48 p64/ec1 general-purpose i/o port. the pin is shared with 8/16-bit compound timer ch.1 clock input. 49 p65/sck general-purpose i/o port. the pin is shared with lin-uart clock i/o. 50 p66/sot general-purpose i/o port. the pin is shared with lin-uart data output. 51 p67/sin l general-purpose i/o port. the pin is shared with lin-uart data input. 52 p43/an11 j general-purpose i/o port. the pins are shared with a/d converter analog input. 53 p42/an10 54 p41/an09 55 p40/an08
mb95100am series 12 ds07-12614-3e (continued) *: for the i/o circuit type, refer to ? i/o circuit type? pin no. pin name i/o circuit type* function 56 p37/an07 j general-purpose i/o port. the pins are shared with a/d converter analog input. 57 p36/an06 58 p35/an05 59 p34/an04 60 p33/an03 61 p32/an02 62 p31/an01 63 p30/an00 64 avss ? a/d converter power supply pin (gnd)
mb95100am series ds07-12614-3e 13 i/o circuit type (continued) type circuit remarks a oscillation circuit high-speed side feedback resistance : approx. 1 m ? low-speed side feedback resistance : approx. 10 m ? b only for input hysteresis input only for mask rom product with pull-down resistor only for mask rom product b? hysteresis input only for mask rom product reset output c cmos output hysteresis input automotive input g cmos output cmos input hysteresis input with pull-up control automotive input x0 (x0a) x1 (x1a) n-ch standby control clock input r mode input n-ch reset input reset output p-ch n-ch standby control external interrupt enable digital output digital output hysteresis input automotive input r p-ch n-ch p-ch pull-up control standby control digital output digital output hysteresis input cmos input automotive input
mb95100am series 14 ds07-12614-3e (continued) type circuit remarks h cmos output hysteresis input with pull-up control automotive input i n-ch open drain output cmos input hysteresis input automotive input j cmos output hysteresis input analog input with pull-up control automotive input k cmos output hysteresis input automotive input p-ch p-ch n-ch r pull-up control standby control digital output digital output hysteresis input automotive input n-ch standby control digital output cmos input hysteresis input automotive input r p-ch p-ch n-ch pull-up control a/d control standby control analog input digital output hysteresis input digital output automotive input p-ch n-ch standby control hysteresis input digital output digital output automotive input
mb95100am series ds07-12614-3e 15 (continued) type circuit remarks l cmos output cmos input hysteresis input automotive input o n-ch open drain output hysteresis input automotive input p cmos output hysteresis input with pull-up control automotive input p-ch n-ch standby control digital output hysteresis input cmos input digital output automotive input n-ch standby control digital output hysteresis input automotive input r p-ch p-ch n-ch standby control external interrupt control pull-up control hysteresis input digital output digital output automotive input
mb95100am series 16 ds07-12614-3e handling devices ? preventing latch-up care must be taken to ensure that maximum vo ltage ratings are not exceeded when they are used. latch-up may occur on cmos ic s if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between v cc pin and v ss pin. when latch-up occurs, power supply current increa ses rapidly and might thermally damage elements. also, take care to prevent the analog power supply voltage (av cc , avr) and analog input voltage from exceeding the digital power supply voltage (v cc ) when the analog system powe r supply is turned on or off. ? stable supply voltage supply voltage should be stabilized. a sudden change in power-supply voltage may cause a ma lfunction even within the guaranteed operating range of the vcc power-supply voltage. for stabilization, in principle, keep the variation in vcc ripple (p-p value) in a commercial frequency range (50 hz/60 hz) not to exceed 10% of the standard vcc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 v/ms du ring a momentary change such as when the power supply is switched. ? precautions for use of external clock even when an external clock is used, oscillation stabilizatio n wait time is required for power-on reset, wake-up from sub clock mode or stop mode. pin connection ? treatment of unused input pin leaving unused input pins unconnected can cause abnorma l operation or latch-up, leaving to permanent dam- age. unused input pins should al ways be pulled up or down through resistance of at least 2 k ? . any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. if there is unused output pin, make it to open. ? treatment of power supply pins on a/d converter connect to be av cc = v cc and av ss = avr = v ss even if the a/d converter is not in use. noise riding on the av cc pin may cause accuracy degradation. so, connect approx. 0.1 f ceramic capacitor as a bypass capacitor between av cc and av ss pins in the vicinity of this device. ? power supply pins in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission le vel, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a cera mic bypass capacitor of approximately 0.1 f between v cc and v ss near this device.
mb95100am series ds07-12614-3e 17 ? mode pin (mod) connect the mod pin directly to v cc or v ss pins. to prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mod pins to v cc or v ss pins and to provide a low-impedance connection. use a ceramic capacitor or a capacitor with equivalent frequency characteristics. a bypass capacitor of v cc pin must have a capacitance value higher than c s . for connection of smoothing capacitor c s , refer to the diagram below. ? analog power supply always set the same potential to av cc and v cc pins. when v cc > av cc , the current may flow through the an00 to an11 pins. c c s c pin connection diagram
mb95100am series 18 ds07-12614-3e programming flash memory microcontrollers using parallel programmer ? supported parallel programmers and adapters the following table lists supported parallel programmers and adapters. note : for information on applicable adapter models and parallel programmers, contact the following: flash support group, inc. tel: + 81-53-428-8380 ? sector configuration the individual sectors of flash memory correspond to addresses used for cpu access and programming by the parallel programmer as follows: ? programming method 1) set the type code of the parallel programmer to ?17222?. 2) load program data to pr ogrammer addresses 71000 h to 7ffff h . 3) programmed by parallel programmer package applicable adapter model parallel programmers fpt-64p-m03 tef110-108f35ap af9708 (ver 02.35g or more) af9709/b (ver 02.35g or more) af9723+af9834 (ver 02.08e or more) fpt-64p-m09 tef110-108f36ap *: programmer addresses are equivalent to cpu addr esses, used when the parallel programmer programs data into flash memory. these programmer addresses are us ed for the parallel programmer to program or erase data in flash memory. flash memory cpu address programmer address* sa1 (4 kbytes) 1000 h 71000 h 1fff h 71fff h sa2 (4 kbytes) 2000 h 72000 h 2fff h 72fff h sa3 (4 kbytes) 3000 h 73000 h 3fff h 73fff h sa4 (16 kbytes) 4000 h 74000 h 7fff h 77fff h sa5 (16 kbytes) 8000 h 78000 h bfff h 7bfff h sa6 (4 kbytes) c000 h 7c000 h cfff h 7cfff h sa7 (4 kbytes) d000 h 7d000 h dfff h 7dfff h sa8 (4 kbytes) e000 h 7e000 h efff h 7efff h sa9 (4 kbytes) f000 h 7f000 h ffff h 7ffff h lower bank upper bank ? mb95f108ams/f108ans/f108ajs/f108 amw/f108anw/f108ajw (60 kbytes)
mb95100am series ds07-12614-3e 19 ? programming method 1) set the type code of the parallel programmer to "17222" 2) load program data to programmer addresses 78000 h to 7ffff h . 3) programmed by parallel programmer ? programming method 1) set the type code of the parallel programmer to "17222" 2) load program data to programmer addresses 7c000 h to 7ffff h . 3) programmed by parallel programmer *: programmer addresses are equivalent to cpu addr esses, used when the parallel programmer programs data into flash memory. these programmer addresses are us ed for the parallel programmer to program or erase data in flash memory. flash memory cpu address programmer address* sa5 (16 kbytes) 8000 h 78000 h bfff h 7bfff h sa6 (4 kbytes) c000 h 7c000 h cfff h 7cfff h sa7 (4 kbytes) d000 h 7d000 h dfff h 7dfff h sa8 (4 kbytes) e000 h 7e000 h efff h 7efff h sa9 (4 kbytes) f000 h 7f000 h ffff h 7ffff h ? mb95f106ams/f106ans/f106ajs/f106a mw/f106anw/f106ajw (32 kbytes) *: programmer addresses are equivalent to cpu addr esses, used when the parallel programmer programs data into flash memory. these programmer addresses are us ed for the parallel programmer to program or erase data in flash memory. flash memory cpu address programmer address* sa6 (4 kbytes) c000 h 7c000 h cfff h 7cfff h sa7 (4 kbytes) d000 h 7d000 h dfff h 7dfff h sa8 (4 kbytes) e000 h 7e000 h efff h 7efff h sa9 (4 kbytes) f000 h 7f000 h ffff h 7ffff h ? mb95f104ams/f104ans/f104ajs/f104a mw/f104anw/f104ajw (16 kbytes)
mb95100am series 20 ds07-12614-3e block diagram p80 to p83 p14/ppg0 p53/trg1 p65/sck p67/sin pe0/int10 to pe3/int13 av cc av ss avr p52/ppg1 p50/scl0 p51/sda0 p40/an08 to p43/an11 p30/an00 to p37/an07 p21/ppg01 p22/to00 p23/to01 p24/ec0 p12/uck0 p62/to10 p61/ppg11 p60/ppg10 p63/to11 p00/int00 to p07/int07 p10/ui0 p64/ec1 p71/ti0 p66/sot p70/to0 rst x0,x1 pg2/x1a* pg1/x0a* mod, v cc , v ss , c p13/trg0/adtg p20/ppg00 p11/uo0 i 2 c f 2 mc-8fx cpu uart/sio 16-bit ppg ch.0 8/16-bit ppg ch.0 8/10-bit a/d converter c 16-bit ppg ch.1 lin-uart 8/16-bit ppg ch.1 rom ram port port external interrupt ch.8 to ch.11 8/16-bit compound timer ch.0 16-bit reload timer 8/16-bit compound timer ch.1 interrupt control wild register reset control clock control watch prescaler watch counter external interrupt ch.0 to ch.7 internal bus * : single clock product is general-purpose port, a nd dual clock product is sub clock oscillation pin. other pins
mb95100am series ds07-12614-3e 21 cpu core 1. memory space memory space of the mb95100am series is 64 kbytes a nd consists of i/o area, data area, and program area. the memory space includes special-purpose areas such as the general-purpose registers and vector table. memory map of the mb95100am series is shown below. memory map 0000 h 00 8 0 h 0100 h 0200 h 0f 8 0 h 1000 h ffff h exten s ion i/o fl as h memory 60 k b yte s ram 3 .75 k b yte s mb95fv100d-10 3 i/o 0000 h 00 8 0 h 0100 h 0200 h addre ss #1 addre ss #2 ffff h fl as h memory mb95f104am s /f104an s /f104aj s mb95f106am s /f106an s /f106aj s mb95f10 8 am s /f10 8 an s /f10 8 aj s mb95f104amw/f104anw/f104ajw mb95f106amw/f106anw/f106ajw mb95f10 8 amw/f10 8 anw/f10 8 ajw i/o ram exten s ion i/o 0000 h 00 8 0 h 0100 h 0200 h 0 88 0 h 0f 8 0 h 1000 h ffff h ma s k rom 60 k b yte s mb9510 8 am i/o ram 2 k b yte s exten s ion i/o regi s ter regi s ter acce ss prohi b ited acce ss prohi b ited regi s ter 0f 8 0 h
mb95100am series 22 ds07-12614-3e flash ram address #1 address #2 mb95f104ams/f104ans/f104ajs 16 kbytes 512 bytes 0280 h c000 h mb95f104amw/f104anw/f104ajw mb95f106ams/f106ans/f106ajs 32 kbytes 1 kbyte 0480 h 8000 h mb95f106amw/f106anw/f106ajw mb95f108ams/f108ans/f108ajs 60 kbytes 2 kbytes 0880 h 1000 h mb95f108amw/f108anw/f108ajw
mb95100am series ds07-12614-3e 23 2. register the mb95100am series has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the dedicated registers are as follows: the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and a direct bank pointer (dp) and the lower 8 bits for use as a condition code register (ccr) . (refer to the diagram below.) program counter (pc) : a 16-bit register to indi cate locations where instructions are stored. accumulator (a) : a 16-bit register for temporary st orage of arithmetic oper ations. in the case of an 8-bit data processing instruction, the lower one byte is used. temporary accumulator (t) : a 16-bit register which pe rforms arithmetic operations with the accumulator. in the case of an 8-bit data processing instruction, the lower one byte is used. index register (ix) : a 16-bit re gister for index modification. extra pointer (ep) : a 16-bit pointer to point to a memory address. stack pointer (sp) : a 16-bit register to indicate a stack area. program status (ps) : a 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register. pc a t ix ep sp ps : program counter 16-bit : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status initial value fffd h 0000 h 0000 h 0000 h 0000 h 0000 h 0030 h ps rp ccr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 dp2 dp1 dp0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r4 r3 r2 r1 r0 h i il1 il0 n z v c dp ? structure of the program status
mb95100am series 24 ds07-12614-3e the rp indicates the address of the register bank cu rrently being used. the relati onship between the content of rp and the real address conforms to the conversion rule illustrated below: the dp specifies the area for mapping instructions (16 di fferent instructions such as mov a, dir) using direct addresses to 0080 h to 00ff h . the ccr consists of the bits indicating arithmetic operat ion results or transfer data contents and the bits that control cpu operations at interrupt. direct bank pointer (dp2 to dp0) specified address area mapping area xxx b (no effect to mapping) 0000 h to 007f h 0000 h to 007f h (without mapping) 000 b (initial value) 0080 h to 00ff h 0080 h to 00ff h (without mapping) 001 b 0100 h to 017f h 010 b 0180 h to 01ff h 011 b 0200 h to 027f h 100 b 0280 h to 02ff h 101 b 0300 h to 037f h 110 b 0380 h to 03ff h 111 b 0400 h to 047f h h flag : set to ?1? when a carry or a borrow from bit 3 to bi t 4 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. this flag is for decimal adjustment instructions. i flag : interrupt is enabled when this flag is set to ?1?. in terrupt is disabled when this flag is set to ?0?. the flag is set to ?0? when reset. il1, il0 : indicates the level of the interrupt currently enabled. processes an inte rrupt only if its request level is higher than the value indicated by this bit. il1 il0 interrupt level priority 00 0 high low = no interruption 01 1 10 2 11 3 n flag : set to ?1? if the msb is set to ?1? as the result of an arithmetic operation. cleared to ?0? when the bit is set to ?0?. z flag : set to ?1? when an arithmetic operation re sults in ?0?. cleared to ?0? otherwise. v flag : set to ?1? if the complement on 2 overflows as a re sult of an arithmetic operation. cleared to ?0? otherwise. c flag : set to ?1? when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. set to the shift-out va lue in the case of a shift instruction. "0" "0" "0" "0" "0" "0" "0" "1" r4 r3 r2 r1 r0 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 a15 a14 a13 a12 a11 a10 a9 a8 ? rule for conversion of actual addresse s in the general-purpose register area generated address rp upper op code lower
mb95100am series ds07-12614-3e 25 the following general-purpose registers are provided: general-purpose registers: 8-bit data storage registers the general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8- registers. up to a total of 32 banks can be used on the mb95100am series. the bank currently in use is specified by the register bank pointer (rp), and the lower 3 bits of op code indicates the general-purpose register 0 (r0) to general-purpose register 7 (r7). r0 r1 r2 r3 r4 r5 r6 r7 r0 this address = 0100 h + 8 (rp) r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 address 100 h 107 h 1f8 h 1ff h bank 31 bank 0 8-bit register bank configuration 32 banks memory area 32 banks (ram area) the number of banks is limited by the usable ram capacitance.
mb95100am series 26 ds07-12614-3e i/o map (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ?? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h pllc pll control register r/w 00000000 b 0007 h sycc system clock control register r/w 1010x011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset source register r xxxxxxxx b 000a h tbtc timebase timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h ? (disabled) ?? 000e h pdr2 port 2 data register r/w 00000000 b 000f h ddr2 port 2 direction register r/w 00000000 b 0010 h pdr3 port 3 data register r/w 00000000 b 0011 h ddr3 port 3 direction register r/w 00000000 b 0012 h pdr4 port 4 data register r/w 00000000 b 0013 h ddr4 port 4 direction register r/w 00000000 b 0014 h pdr5 port 5 data register r/w 00000000 b 0015 h ddr5 port 5 direction register r/w 00000000 b 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h pdr7 port 7 data register r/w 00000000 b 0019 h ddr7 port 7 direction register r/w 00000000 b 001a h pdr8 port 8 data register r/w 00000000 b 001b h ddr8 port 8 direction register r/w 00000000 b 001c h to 0025 h ? (disabled) ?? 0026 h pdre port e data register r/w 00000000 b 0027 h ddre port e direction register r/w 00000000 b 0028 h , 0029 h ? (disabled) ?? 002a h pdrg port g data register r/w 00000000 b
mb95100am series ds07-12614-3e 27 (continued) address register abbreviation register name r/w initial value 002b h ddrg port g direction register r/w 00000000 b 002c h ? (disabled) ?? 002d h pul1 port 1 pull-up register r/w 00000000 b 002e h pul2 port 2 pull-up register r/w 00000000 b 002f h pul3 port 3 pull-up register r/w 00000000 b 0030 h pul4 port 4 pull-up register r/w 00000000 b 0031 h pul5 port 5 pull-up register r/w 00000000 b 0032 h pul7 port 7 pull-up register r/w 00000000 b 0033 h ? (disabled) ?? 0034 h pule port e pull-up register r/w 00000000 b 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit compound timer 01 control status register 1 ch.0 r/w 00000000 b 0037 h t00cr1 8/16-bit compound timer 00 control status register 1 ch.0 r/w 00000000 b 0038 h t11cr1 8/16-bit compound timer 11 control status register 1 ch.1 r/w 00000000 b 0039 h t10cr1 8/16-bit compound timer 10 control status register 1 ch.1 r/w 00000000 b 003a h pc01 8/16-bit ppg1 control register ch.0 r/w 00000000 b 003b h pc00 8/16-bit ppg0 control register ch.0 r/w 00000000 b 003c h pc11 8/16-bit ppg1 control register ch.1 r/w 00000000 b 003d h pc10 8/16-bit ppg0 control register ch.1 r/w 00000000 b 003e h tmcsrh0 16-bit reload timer control status register (upper byte) ch.0 r/w 00000000 b 003f h tmcsrl0 16-bit reload timer control status register (lower byte) ch.0 r/w 00000000 b 0040 h , 0041 h ? (disabled) ?? 0042 h pcnth0 16-bit ppg status control r egister (upper byte) ch.0 r/w 00000000 b 0043 h pcntl0 16-bit ppg status control regi ster (lower byte) ch.0 r/w 00000000 b 0044 h pcnth1 16-bit ppg status control r egister (upper byte) ch.1 r/w 00000000 b 0045 h pcntl1 16-bit ppg status control regi ster (lower byte) ch.1 r/w 00000000 b 0046 h , 0047 h ? (disabled) ?? 0048 h eic00 external interrupt circuit control register ch.0/ch.1 r/w 00000000 b 0049 h eic10 external interrupt circuit control register ch.2/ch.3 r/w 00000000 b 004a h eic20 external interrupt circuit control register ch.4/ch.5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch.6/ch.7 r/w 00000000 b 004c h eic01 external interrupt circuit control register ch.8/ch.9 r/w 00000000 b 004d h eic11 external interrupt circuit cont rol register ch.10/ch.11 r/w 00000000 b
mb95100am series 28 ds07-12614-3e (continued) address register abbreviation register name r/w initial value 004e h , 004f h ? (disabled) ?? 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial status register r/w 00001000 b 0053 h rdr/tdr lin-uart reception/transmission data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communicat ion control register r/w 000000xx b 0056 h smc10 uart/sio serial mode cont rol register 1 ch.0 r/w 00000000 b 0057 h smc20 uart/sio serial mode c ontrol register 2 ch.0 r/w 00100000 b 0058 h ssr0 uart/sio serial status register ch.0 r/w 00000001 b 0059 h tdr0 uart/sio serial output data register ch.0 r/w 00000000 b 005a h rdr0 uart/sio serial input data register ch.0 r 00000000 b 005b h to 005f h ? (disabled) ?? 0060 h ibcr00 i 2 c bus control register 0 ch.0 r/w 00000000 b 0061 h ibcr10 i 2 c bus control register 1 ch.0 r/w 00000000 b 0062 h ibsr0 i 2 c bus status register ch.0 r 00000000 b 0063 h iddr0 i 2 c data register ch.0 r/w 00000000 b 0064 h iaar0 i 2 c address register ch.0 r/w 00000000 b 0065 h iccr0 i 2 c clock control regi ster ch.0 r/w 00000000 b 0066 h to 006b h ? (disabled) ?? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register (upper byte) r/w 00000000 b 006f h addl 8/10-bit a/d converter data register (lower byte) r/w 00000000 b 0070 h wcsr watch counter status register r/w 00000000 b 0071 h ? (disabled) ?? 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector writ ing control register 0 r/w 00000000 b 0074 h swre1 flash memory sector writ ing control register 1 r/w 00000000 b 0075 h ? (disabled) ?? 0076 h wren wild register address co mpare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b
mb95100am series ds07-12614-3e 29 (continued) address register abbreviation register name r/w initial value 0078 h ? mirror of register bank pointer (rp) and direct bank pointer (dp) ?? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ?? 0f80 h wrarh0 wild register address setting register (upper byte) ch.0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower byte) ch.0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch.0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper byte) ch.1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower byte) ch.1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch.1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper byte) ch.2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower byte) ch.2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch.2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ?? 0f92 h t01cr0 8/16-bit compound timer 01 cont rol status register 0 ch.0 r/w 00000000 b 0f93 h t00cr0 8/16-bit compound timer 00 cont rol status register 0 ch.0 r/w 00000000 b 0f94 h t01dr 8/16-bit compound timer 01 data register ch.0 r/w 00000000 b 0f95 h t00dr 8/16-bit compound timer 00 data register ch.0 r/w 00000000 b 0f96 h tmcr0 8/16-bit compound timer 00/01 timer mode control register ch.0 r/w 00000000 b 0f97 h t11cr0 8/16-bit compound timer 11 cont rol status register 0 ch.1 r/w 00000000 b 0f98 h t10cr0 8/16-bit compound timer 10 cont rol status register 0 ch.1 r/w 00000000 b 0f99 h t11dr 8/16-bit compound timer 11 data register ch.1 r/w 00000000 b 0f9a h t10dr 8/16-bit compound timer 10 data register ch.1 r/w 00000000 b 0f9b h tmcr1 8/16-bit compound timer 10/11 timer mode control register ch.1 r/w 00000000 b 0f9c h pps01 8/16-bit ppg1 cycle setting buffer register ch.0 r/w 11111111 b 0f9d h pps00 8/16-bit ppg0 cycle setting buffer register ch.0 r/w 11111111 b 0f9e h pds01 8/16-bit ppg1 duty setting buffer register ch.0 r/w 11111111 b 0f9f h pds00 8/16-bit ppg0 duty setting buffer register ch.0 r/w 11111111 b
mb95100am series 30 ds07-12614-3e (continued) address register abbreviation register name r/w initial value 0fa0 h pps11 8/16-bit ppg1 cycle setting buffer register ch.1 r/w 11111111 b 0fa1 h pps10 8/16-bit ppg0 cycle setting buffer register ch.1 r/w 11111111 b 0fa2 h pds11 8/16-bit ppg1 duty setting buffer register ch.1 r/w 11111111 b 0fa3 h pds10 8/16-bit ppg0 duty setting buffer register ch.1 r/w 11111111 b 0fa4 h ppgs 8/16-bit ppg start register r/w 00000000 b 0fa5 h revc 8/16-bit ppg output inversion register r/w 00000000 b 0fa6 h tmrh0/ tmrlrh0 16-bit timer register (upper byte) ch.0/ 16-bit reload register (upper byte) ch.0 r/w 00000000 b 0fa7 h tmrl0/ tmrlrl0 16-bit timer register (lower byte) ch.0/ 16-bit reload register (lower byte) ch.0 r/w 00000000 b 0fa8 h , 0fa9 h ? (disabled) ?? 0faa h pdcrh0 16-bit ppg down counter re gister (upper byte) ch.0 r 00000000 b 0fab h pdcrl0 16-bit ppg down counter register (lower byte) ch.0 r 00000000 b 0fac h pcsrh0 16-bit ppg cycle setting buffer register (upper byte) ch.0 r/w 11111111 b 0fad h pcsrl0 16-bit ppg cycle setting buffer register (lower byte) ch.0 r/w 11111111 b 0fae h pduth0 16-bit ppg duty setting buffer re gister (upper byte) ch.0 r/w 11111111 b 0faf h pdutl0 16-bit ppg duty setting buffer re gister (lower byte) ch.0 r/w 11111111 b 0fb0 h pdcrh1 16-bit ppg down counter re gister (upper byte) ch.1 r 00000000 b 0fb1 h pdcrl1 16-bit ppg down counter register (lower byte) ch.1 r 00000000 b 0fb2 h pcsrh1 16-bit ppg cycle setting buffer register (upper byte) ch.1 r/w 11111111 b 0fb3 h pcsrl1 16-bit ppg cycle setting buffer register (lower byte) ch.1 r/w 11111111 b 0fb4 h pduth1 16-bit ppg duty setting buffer register ( upper byte ) ch.1 r/w 11111111 b 0fb5 h pdutl1 16-bit ppg duty setting buffer register ( lower byte ) ch.1 r/w 11111111 b 0fb6 h to 0fbb h ? (disabled) ?? 0fbc h bgr1 lin-uart baud rate gener ator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate generator register 0 r/w 00000000 b 0fbe h pssr0 uart/sio dedicated baud rate generator prescaler selection register ch.0 r/w 00000000 b 0fbf h brsr0 uart/sio dedicated baud rate generator baud rate setting register ch.0 r/w 00000000 b 0fc0 h , 0fc1 h ? (disabled) ?? 0fc2 h aidrh a/d input disable register (upper byte) r/w 00000000 b 0fc3 h aidrl a/d input disable register (lower byte) r/w 00000000 b
mb95100am series ds07-12614-3e 31 (continued) ? r/w access symbols ? initial value symbols note : do not write to the ? (d isabled) ?. reading the ? (disabl ed) ? returns an undefined value. address register abbreviation register name r/w initial value 0fc4 h to 0fe2 h ? (disabled) ?? 0fe3 h wcdr watch counter data register r/w 00111111 b 0fe4 h to 0fe6 h ? (disabled) ?? 0fe7 h ilsr2 input level select register 2 r/w 00000000 b 0fe8 h , 0fe9 h ? (disabled) ?? 0fea h csvcr clock supervisor control register r/w 00011100 b 0feb h to 0fed h ? (disabled) ?? 0fee h ilsr input level select register r/w 00000000 b 0fef h wicr interrupt pin control register r/w 01000000 b 0ff0 h to 0fff h ? (disabled) ?? r/w : readable/writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95100am series 32 ds07-12614-3e interrupt source table interrupt source interrupt request number vector table address bit name of interrupt level setting register same level priority order (at simultaneous occurrence) upper lower external interrupt ch.0 irq0 fffa h fffb h l00 [1 : 0] high external interrupt ch.4 external interrupt ch.1 irq1 fff8 h fff9 h l01 [1 : 0] external interrupt ch.5 external interrupt ch.2 irq2 fff6 h fff7 h l02 [1 : 0] external interrupt ch.6 external interrupt ch.3 irq3 fff4 h fff5 h l03 [1 : 0] external interrupt ch.7 uart/sio ch.0 irq4 fff2 h fff3 h l04 [1 : 0] 8/16-bit compound timer ch.0 (lower) irq5 fff0 h fff1 h l05 [1 : 0] 8/16-bit compound timer ch.0 (upper) irq6 ffee h ffef h l06 [1 : 0] lin-uart (reception) irq7 ffec h ffed h l07 [1 : 0] lin-uart (transmission) irq8 ffea h ffeb h l08 [1 : 0] 8/16-bit ppg ch.1 (lower) irq9 ffe8 h ffe9 h l09 [1 : 0] 8/16-bit ppg ch.1 (upper) irq10 ffe6 h ffe7 h l10 [1 : 0] 16-bit reload timer ch.0 irq11 ffe4 h ffe5 h l11 [1 : 0] 8/16-bit ppg ch.0 (upper) irq12 ffe2 h ffe3 h l12 [1 : 0] 8/16-bit ppg ch.0 (lower) irq13 ffe0 h ffe1 h l13 [1 : 0] 8/16-bit compound timer ch.1 (upper) irq14 ffde h ffdf h l14 [1 : 0] 16-bit ppg ch.0 irq15 ffdc h ffdd h l15 [1 : 0] i 2 c ch.0 irq16 ffda h ffdb h l16 [1 : 0] 16-bit ppg ch.1 irq17 ffd8 h ffd9 h l17 [1 : 0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1 : 0] timebase timer irq19 ffd4 h ffd5 h l19 [1 : 0] watch prescaler/watch counter irq20 ffd2 h ffd3 h l20 [1 : 0] external interrupt ch.8 irq21 ffd0 h ffd1 h l21 [1 : 0] external interrupt ch.9 external interrupt ch.10 external interrupt ch.11 8/16-bit compound timer ch.1 (lower) irq22 ffce h ffcf h l22 [1 : 0] flash memory irq23 ffcc h ffcd h l23 [1 : 0] low
mb95100am series ds07-12614-3e 33 electrical characteristics 1. absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 vcc avcc vss ? 0.3 vss + 6.0 v *2 avr vss ? 0.3 vss + 6.0 *2 input voltage* 1 v i vss ? 0.3 vss + 6.0 *3 output voltage* 1 v o vss ? 0.3 vss + 6.0 v *3 maximum clamp current i clamp ? 2.0 + 2.0 ma applicable to pins* 4 total maximum clamp current |i clamp | ? 20 ma applicable to pins* 4 ?l? level maximum output current i ol1 ? 15 ma other than p00 to p07 i ol2 15 p00 to p07 ?l? level average current i olav1 ? 4 ma other than p00 to p07 average output current = operating current operating ratio (1 pin) i olav2 12 p00 to p07 average output current = operating current operating ratio (1 pin) ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma total average output current = operating current operating ratio (total of pins) ?h? level maximum output current i oh1 ? ? 15 ma other than p00 to p07 i oh2 ? 15 p00 to p07 ?h? level average current i ohav1 ? ? 4 ma other than p00 to p07 average output current = operating current operating ratio (1 pin) i ohav2 ? 8 p00 to p07 average output current = operating current operating ratio (1 pin) ?h? level total maximum output current i oh ? ? 100 ma ?h? level total average output current i ohav ? ? 50 ma total average output current = operating current operating ratio (total of pins)
mb95100am series 34 ds07-12614-3e (continued) *1 : the parameter is based on av ss = v ss = 0.0 v. *2 : apply equal potential to avcc an d vcc. avr should not exceed avcc + 0.3 v. *3 : v i and vo should not exceed v cc + 0.3 v. v i must not exceed the rating voltage. however, if the maximum current to/from an input is limited by some m eans with external components, the i clamp rating supersedes the v i rating. *4 : applicable to pins : p00 to p07, p10 to p14, p20 to p24, p30 to p37, p40 to p43, p52, p53, p70, p71, pe0 to pe3 ? use within recommended operating conditions. ? use at dc voltage (current). ? + b signal is an input signal that exceeds v cc voltage. the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated va lues, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is lo w, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potential at the v cc pin, and this affect other devices. ? note that if the + b signal is inputted when the mi crocontroller power supply is off (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the powe r supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? sample recommended circuits : warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. parameter symbol rating unit min max power consumption pd ? 320 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c p-ch n-ch vcc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb95100am series ds07-12614-3e 35 2. recommended operating conditions (avss = vss = 0.0 v) *1 : the value is 2.88 v when the low voltage detection reset is used. *2 : use a ceramic capacitor or a capacitor with equiva lent frequency characteristics. a bypass capacitor of v cc pin must have a capacitan ce value higher than c s . for connection of smoothing capacitor c s , refer to the diagram below. warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outs ide the listed conditions are advised to contact their representatives beforehand. parameter sym- bol pin name conditions value unit remarks min max power supply voltage v cc , av cc ?? 2.42* 1 5.5 v at normal operating other than mb95fv100d-103 2.3 5.5 retain status of stop operation 2.7 5.5 at normal operating mb95fv100d-103 2.3 5.5 retain status of stop operation a/d converter reference input voltage avr ?? 4.0 av cc v smoothing capacitor c s ?? 0.1 1.0 f*2 operating temperature t a ?? ? 40 + 85 c other than mb95fv100d-103 + 5 + 35 mb95fv100d-103 c c s c pin connection diagram
mb95100am series 36 ds07-12614-3e 3. dc characteristics (vcc = avcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max ?h? level input voltage v ih p10, p50, p51, p67 *1 0.7 vcc ? vcc + 0.3 v hysteresis input of cmos input level v iha p00 to p07, p10 to p14, p20 to p24, p30 to p37, p40 to p43, p50 to p53, p60 to p67, p70, p71, p80 to p83, pe0 to pe3, pg1* 2 , pg2* 2 ? 0.8 v cc ? v cc + 0.3 v pin input at selecting of automotive input level v ihs p00 to p07, p10 to p14, p20 to p24, p30 to p37, p40 to p43, p50 to p53, p60 to p67, p70, p71, p80 to p83, pe0 to pe3, pg1* 2 , pg2* 2 *1 0.8 vcc ? vcc + 0.3 v hysteresis input v ihm rst , mod ? 0.7 vcc ? vcc + 0.3 v cmos input (mask rom product is hysteresis input) ?l? level input voltage v il p10, p50, p51, p67 *1 vss ? 0.3 ? 0.3 vcc v hysteresis input of cmos input level v ila p00 to p07, p10 to p14, p20 to p24, p30 to p37, p40 to p43, p50 to p53, p60 to p67, p70, p71, p80 to p83, pe0 to pe3, pg1* 2 , pg2* 2 ? v ss ? 0.3 ? 0.5 v cc v pin input at selecting of automotive input level v ils p00 to p07, p10 to p14, p20 to p24, p30 to p37, p40 to p43, p50 to p53, p60 to p67, p70, p71, p80 to p83, pe0 to pe3, pg1* 2 , pg2* 2 *1 vss ? 0.3 ? 0.2 vcc v hysteresis input v ilm rst , mod ? vss ? 0.3 ? 0.3 vcc v cmos input (mask rom product is hysteresis input)
mb95100am series ds07-12614-3e 37 (vcc = avcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max open-drain output application voltage v d p50, p51, p80 to p83 ? vss ? 0.3 ? vss + 5.5 v ?h? level output voltage v oh1 output pin other than p00 to p07 i oh = ? 4.0 ma v cc ? 0.5 ?? v v oh2 p00 to p07 i oh = ? 8.0 ma v cc ? 0.5 ?? v ?l? level output voltage v ol1 output pin other than p00 to p07, rst * 3 i ol = 4.0 ma ?? 0.4 v v ol2 p00 to p07 i ol = 12 ma ?? 0.4 v input leakage current (hi-z output leakage current) i li port other than p50, p51, p80 to p83 0.0 v < v i < vcc ? 5 ? + 5 a when the pull-up prohibition setting open-drain output leakage current i liod p50, p51, p80 to p83 0.0 v < v i < vss + 5.5 v ?? 5 a pull-up resistor r pull p10 to p14,p20 to p24, p30 to p37, p40 to p43, p52, p53, p70, p71, pe0 to pe3, pg1* 2 , pg2* 2 v i = 0.0 v 25 50 100 k ? when the pull-up permission setting pull-down resistor r mod mod v i = vcc 25 50 100 k ? mask rom product input capacitance c in other than avcc, avss, avr, vcc, vss f = 1 mhz ? 515pf power supply current* 4 i cc vcc (external clock operation) v cc = 5.5 v f ch = 20 mhz f mp = 10 mhz main clock mode (divided by 2) ? 9.5 12.5 ma flash memory product (at other than writing and erasing) ? 30 35 ma flash memory product (at writing and erasing) ? 7.2 9.5 ma mask rom product f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ? 15.2 20.0 ma flash memory product (at other than writing and erasing) ? 35.7 42.5 ma flash memory product (at writing and erasing) ? 11.6 15.2 ma mask rom product
mb95100am series 38 ds07-12614-3e (vcc = avcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c ) (continued) parameter sym- bol pin name conditions value unit remarks min typ max power supply current* 4 i ccs vcc (external clock operation) v cc = 5.5 v f ch = 20 mhz f mp = 10 mhz main sleep mode (divided by 2) ? 4.5 7.5 ma f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ? 7.2 12.0 ma i ccl v cc = 5.5 v f cl = 32 khz f mpl = 16 khz sub clock mode (divided by 2) , t a = + 25 c ? 45 100 a dual clock product only i ccls v cc = 5.5 v f cl = 32 khz f mpl = 16 khz sub sleep mode (divided by 2) , t a = + 25 c ? 10 81 a dual clock product only i cct v cc = 5.5 v f cl = 32 khz watch mode main stop mode t a = + 25 c ? 4.6 27.0 a dual clock product only i ccmpll v cc = 5.5 v f ch = 4 mhz f mp = 10 mhz main pll mode (multiplied by 2.5) ? 9.3 12.5 ma flash memory product ? 7.0 9.5 ma mask rom product f ch = 6.4 mhz f mp = 16 mhz main pll mode (multiplied by 2.5) ? 14.9 20.0 ma flash memory product ? 11.2 15.2 ma mask rom product i ccspll v cc = 5.5 v f cl = 32 khz f mpl = 128 khz sub pll mode ( multiplied by 4 ) , t a = + 25 c ? 160 400 a dual clock product only
mb95100am series ds07-12614-3e 39 (continued) (vcc = avcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : p10, p50, p51, and p67 can switch the input level to either the ?cmos input level? or ?hysteresis input level?. the switching of the input level can be set by the input level selection register (ilsr). *2 : single clock products only *3 : product without clock supervisor only *4 : ? the power-supply current is determined by the external clock. when the low volt age detection option is selected, the power-supply current will be a value of ad ding current consumption of the low voltage detection circuit (i lv d ) to the specified value. also, when both low voltage detection option and clock supervisor are selected, the power-supply current will be a value of ad ding current consumption of the low voltage detection circuit (i lv d ) and current consumption of internal cr oscillator (i csv ) to the specified value. ? refer to ?4. ac characteristics (1) clock timing? for f ch and f cl . ? refer to ?4. ac characteristics (2) source clock/machine clock? for f mp and f mpl . parameter sym- bol pin name conditions value unit remarks min typ max power supply current* 4 i cts v cc (external clock operation) v cc = 5.5 v f ch = 10 mhz timebase timer mode t a = + 25 c ? 0.15 1.10 ma i cch v cc = 5.5 v sub stop mode t a = + 25 c ? 3.5 20 a main stop mode for single clock product i lvd v cc current consumption for low voltage detection circuit only ? 38 50 a i csv at oscillating 100 khz current consumption of internal cr oscillator ? 20 36 a i a avcc v cc = 5.5 v f ch = 16 mhz at operating of a/d conversion ? 2.4 4.7 ma i ah v cc = 5.5 v f ch = 16 mhz at stopping a/d conversion t a = + 25 c ? 15 a
mb95100am series 40 ds07-12614-3e 4. ac characteristics (1) clock timing (vcc = 2.42 v to 5.0 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol pin name condi- tions value unit remarks min typ max clock frequency f ch x0, x1 ? 1.00 ? 16.25 mhz when using main oscillation circuit 1.00 ? 32.50 mhz when using external clock 3.00 ? 10.00 mhz main pll multiplied by 1 3.00 ? 8.13 mhz main pll multiplied by 2 3.00 ? 6.50 mhz main pll multiplied by 2.5 f cl x0a, x1a ? 32.768 ? khz when using sub oscillation circuit ? 32.768 ? khz when using sub pll clock cycle time t hcyl x0, x1 61.5 ? 1000 ns when using oscillation circuit 30.8 ? 1000 ns when using external clock t lcyl x0a, x1a ? 30.5 ? s when using sub clock input clock pulse width t wh1 t wl1 x0 61.5 ?? ns when using external clock duty ratio is about 30 % to 70 % . t wh2 t wl2 x0a ? 15.2 ? s input clock rise time and fall time t cr t cf x0, x0a ?? 5 ns when using external clock
mb95100am series ds07-12614-3e 41 t hcyl t wh1 t cr 0.2 v cc x0 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t cf t wl1 x0 x1 f ch x0 f ch x1 ? figure of main clock input port external connection when using a crystal or ceramic oscillator when using external clock open microcontroller microcontroller t lcyl t wh2 t cr 0.1 v cc x0a 0.8 v cc 0.8 v cc 0.1 v cc 0.1 v cc t cf t wl2 x0a x1a f cl x0a f cl x1a ? figure of sub clock input port external connection when using a crystal or ceramic oscillator when using external clock open microcontroller microcontroller
mb95100am series 42 ds07-12614-3e (2) source clock/machine clock (vcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : clock before setting division due to machine clock divi sion ratio selection bit (sycc : div1 and div0) . this source clock is divided by the machine clock divisi on ratio selection bit (sycc : div1 and div0) , and it becomes the machine clock. further, the s ource clock can be selected as follows. ? main clock divided by 2 ? pll multiplication of main clock (sel ect from 1, 2, 2.5 multiplication) ? sub clock divided by 2 ? pll multiplication of sub clock (sel ect from 2, 3, 4 multiplication) * 2 : operation clock of the microcontroller. machine clock can be selected as follows. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter sym- bol pin name value unit remarks min typ max source clock* 1 (clock before setting division) t sclk ? 61.5 ? 2000 ns when using main clock min : f ch = 16.25 mhz, pll multiplied by 1 max : f ch = 1 mhz, divided by 2 7.6 ? 61.0 s when using sub clock min : f cl = 32 khz, pll multiplied by 4 max : f cl = 32 khz, divided by 2 source clock frequency f sp ? 0.50 ? 16.25 mhz when using main clock f spl ? 16.384 ? 131.072 khz when using sub clock machine clock* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when using main clock min : f sp = 16.25 mhz, no division max : f sp = 0.5 mhz, divided by 16 7.6 ? 976.5 s when using sub clock min : f spl = 131 khz, no division max : f spl = 16 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.250 mhz when using main clock f mpl 1.024 ? 131.072 khz when using sub clock
mb95100am series ds07-12614-3e 43 f ch (main oscillation) f cl (sub oscillation) divided by 2 main pll 1 2 2.5 divided by 2 sub pll 2 3 4 sclk ( source clock ) mclk ( machine clock ) clock mode select bit ( sycc : scs1, scs0 ) division circuit 1 1/4 1/8 1/16 ? outline of clock generation block
mb95100am series 44 ds07-12614-3e 16.25 mhz 0.5 mhz 2.42 3 mhz 5.5 1 3 1.072 khz 16. 38 4 khz 2.42 3 2 khz 5.5 10 mhz 3 .5 operating voltage (v) source clock frequency (f spl ) main clock operating guarantee range sub pll, sub clock mode, watch mode, operating guarantee range main clock mode, main pll mode operating guarantee range pll operating guarantee range pll operating guarantee range operating voltage (v) source clock frequency (f sp ) ? operating voltage ? operating frequency ( t a = ? 40 c to + 85 c) ? mb95f104ams/f104ans/f104ajs/f106ams/f106an s/f106ajs/f108ams/f108ans/f108ajs/f104amw/ mb95f104anw/f104ajw/f106amw/f106an w/f106ajw/f108amw/f108anw/f108ajw ? operating voltage ? operating frequency ( t a = + 5 c to + 35 c) ? mb95fv100d-103 2.7 5.5 131.072 khz 16.384 khz 2.7 32 khz 5.5 16.25 mhz 0.5 mhz 3 mhz 10 mhz 3.5 source clock frequency (f spl ) operating voltage (v) sub pll, sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range main clock mode and main pll mode operation guarantee range
mb95100am series ds07-12614-3e 45 10 mhz 9 mhz 8 mhz 7.5mhz 7 mhz 6 mhz 5 mhz 4 mhz 3 mhz 0 mhz 3 mhz 4 mhz 5 mhz 6.4 mhz 8 mhz 10 mhz 11 mhz 12 mhz 1 3 mhz 14 mhz 15 mhz 16 mhz ? main pll operation frequency main clock frequency ( f mp ) source clock frequency (f sp ) 2.5 2 1
mb95100am series 46 ds07-12614-3e (3) external reset (vcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : refer to ? (2) source clock/machine clock? for t mclk . *2 : oscillation time of oscillator is the time that the am plitude reaches 90 %. in the crystal oscillator, the oscillation time is between several ms and tens of ms. in ceramic oscillators, the oscillation time is between hundreds of s and several ms. in the external clock, the oscillation time is 0 ms. parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * 1 ? ns at normal operating oscillation time of oscillator* 2 + 100 ? s at stop mode, sub clock mode, sub sleep mode, and watch mode 100 ? s at timebase timer mode t rstl 0.2 v cc rst 0.2 v cc t rstl 0.2 v cc 0.2 v cc 100 s rst x0 ? at normal operating ? at stop mode, sub clock mode, su b sleep mode, watch mode, and power-on internal operating clock internal reset 90 % of amplitude oscillation time of oscillator oscillation stabilization wait time execute instruction
mb95100am series ds07-12614-3e 47 (4) power-on reset (avss = vss = 0.0 v, t a = ? 40 c to + 85 c) note : sudden change of power supply voltage may acti vate the power-on reset function. when changing power supply voltages during operation, set the slope of rising wi thin 30 mv/ms as shown below . parameter symbol conditions value unit remarks min max power supply rising time t r ?? 50 ms power supply cutoff time t off ? 1 ? ms waiting time until power-on 0.2 v 0.2 v t off t r 2.5 v 0.2 v v cc v cc 2.3 v v ss hold condition in stop mode limiting the slope of rising within 30 mv/ms is recommended.
mb95100am series 48 ds07-12614-3e (5) peripheral input timing (vcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int00 to int07, int10 to int13, ec0, ec1, ti0, trg0/adtg, trg1 2 t mclk * ? ns peripheral input ?l? pulse width t ihil 2 t mclk * ? ns t ilih int00 to int07, int10 to int13, ec0, ec1, ti0, trg0/adtg, trg1 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ihil
mb95100am series ds07-12614-3e 49 (6) uart/sio, serial i/o timing (vcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name conditions value unit min max serial clock cycle time t scyc uck0 internal clock operation 4 t mclk * ? ns uck uo time t slov uck0, uo0 ? 190 + 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns serial clock ?h? pulse width t shsl uck0 external clock operation 4 t mclk * ? ns serial clock ?l? pulse width t slsh uck0 4 t mclk * ? ns uck uo time t slov uck0, uo0 ? 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns t scyc t ivsh 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t shix t slov 0.8 v 2.4 v 0.8 v 2.4 v uck0 uo0 ui0 0.8 v t slsh t ivsh t shix t slov 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t shsl 2.4 v uck0 uo0 ui0 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc internal shift clock mode external shift clock mode
mb95100am series 50 ds07-12614-3e (7) lin-uart timing sampling at the rising edge of sampling clock *1 and prohibited serial clock delay *2 (escr register : sces bit = 0, eccr register : scde bit = 0) (vcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of recepti on data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay ha lf clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin : c l = 80 pf + 1 ttl. 3 t mclk * 3 ? t r ? ns serial clock ?h? pulse width t shsl sck t mclk * 3 + 95 ? ns sck sot delay time t slove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivshe sck, sin 190 ? ns sck valid sin hold time t shixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95100am series ds07-12614-3e 51 0.8 v 0.8 v 2.4 v t slovi t ivshi t shixi 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 2.4 v 0.8 v sck sot sin t scyc t slove t ivshe t shixe 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc 2.4 v 0.8 v t r t f sck sot sin t slsh t shsl internal shift clock mode external shift clock mode
mb95100am series 52 ds07-12614-3e sampling at the falling edge of sampling clock *1 and prohibited serial clock delay *2 (escr register : sces bit = 1, eccr register : scde bit = 0) (vcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of recept ion data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin : c l = 80 pf + 1 ttl. 3 t mclk * 3 ? t r ? ns serial clock ?l? pulse width t slsh sck t mclk * 3 + 95 ? ns sck sot delay time t shove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivsle sck, sin 190 ? ns sck valid sin hold time t slixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95100am series ds07-12614-3e 53 0.8 v 2.4 v 2.4 v t shovi t ivsli t slixi 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 2.4 v 0.8 v sck sot sin t scyc t shove t ivsle t slixe 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc 2.4 v 0.8 v t f t r sck sot sin t shsl t slsh internal shift clock mode external shift clock mode
mb95100am series 54 ds07-12614-3e sampling at the rising edge of sampling clock *1 and enabled serial clock delay *2 (escr register : sces bit = 0, eccr register : scde bit = 1) (vcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of recepti on data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay ha lf clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns sot sck delay time t sovli sck, sot ? 4 t mclk * 3 ns sck sot sin 2.4 v 0.8 v 0.8 v t shovi 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 2.4 v 0.8 v t scyc t sovli t ivsli t slixi
mb95100am series ds07-12614-3e 55 sampling at the falling edge of sampling clock *1 and enabled serial clock delay *2 (escr register : sces bit = 1, eccr register : scde bit = 1) (vcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of recept ion data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operating output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns sot sck delay time t sovhi sck, sot ? 4 t mclk * 3 ns sck sot sin 2.4 v 2.4 v 0.8 v t slovi 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 2.4 v 0.8 v t scyc t sovhi t ivshi t shixi
mb95100am series 56 ds07-12614-3e (8) i 2 c timing (vcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : r, c : pull-up resistor and load capacitor of the scl and sda lines. *2 : the maximum t hd;dat have only to be met if the device dose not stretch the ?l? width (t low ) of the scl signal. *3 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. parameter symbol pin name conditions value unit standard- mode fast-mode min max min max scl clock frequency f scl scl0 r = 1.7 k ? , c = 50 pf* 1 0 100 0 400 khz (repeat) start condition hold time sda scl t hd;sta scl0 sda0 4.0 ? 0.6 ? s scl clock ?l? width t low scl0 4.7 ? 1.3 ? s scl clock ?h? width t high scl0 4.0 ? 0.6 ? s (repeat) start condition setup time scl sda t su;sta scl0 sda0 4.7 ? 0.6 ? s data hold time scl sda t hd;dat scl0 sda0 03.45* 2 00.9* 3 s data setup time sda scl t su;dat scl0 sda0 0.25 ? 0.1 ? s stop condition setup time scl sda t su;sto scl0 sda0 4 ? 0.6 ? s bus free time between stop condition and start condition t buf scl0 sda0 4.7 ? 1.3 ? s sda0 scl0 t wakeup t hd;sta t su;dat t hd;sta t su;sta t low t hd;dat t high t su;sto t buf
mb95100am series ds07-12614-3e 57 (vcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name condition value* 2 unit remarks min max scl clock ?l? width t low scl0 r = 1.7 k ? , c = 50 pf* 1 (2 + nm / 2) t mclk ? 20 ? ns master mode scl clock ?h? width t high scl0 (nm / 2) t mclk ? 20 (nm / 2 ) t mclk + 20 ns master mode start condition hold time t hd;sta scl0 sda0 ( ? 1 + nm / 2) t mclk ? 20 ( ? 1 + nm) t mclk + 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto scl0 sda0 (1 + nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns master mode start condition setup time t su;sta scl0 sda0 (1 + nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns master mode bus free time between stop condition and start condition t buf scl0 sda0 (2 nm + 4) t mclk ? 20 ? ns data hold time t hd;dat scl0 sda0 3 t mclk ? 20 ? ns master mode data setup time t su;dat scl0 sda0 ( ? 2 + nm / 2) t mclk ? 20 ( ? 1 + nm / 2) t mclk + 20 ns master mode when assuming that ?l? of scl is not extended, the minimum value is applied to first bit of continuous data. otherwise, the maximum value is applied. setup time between clearing interrupt and scl rising t su;int scl0 (nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns minimum value is applied to interrupt at 9th scl . maximum value is applied to interrupt at 8th scl . scl clock ?l? width t low scl0 4 t mclk ? 20 ? ns at reception scl clock ?h? width t high scl0 4 t mclk ? 20 ? ns at reception start condition detection t hd;sta scl0 sda0 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception stop condition detection t su;sto scl0 sda0 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception restart detection condition t su;sta scl0 sda0 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception bus free time t buf scl0 sda0 2 t mclk ? 20 ? ns at reception data hold time t hd;dat scl0 sda0 2 t mclk ? 20 ? ns at slave transmission mode data setup time t su;dat scl0 sda0 t low ? 3 t mclk ? 20 ? ns at slave transmission mode
mb95100am series 58 ds07-12614-3e (continued) (vcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) *1 : r, c : pull-up resistor and load capacitor of the scl and sda lines. *2 : ? refer to ? (2) source clock/machine clock? for t mclk . ? m is cs4 bit and cs3 bit (bit 4 and bit 3) of clock control register (iccr0) . ? n is cs2 bit to cs0 bit (bit 2 to bit 0) of clock control register (iccr0) . ? actual timing of i 2 c is determined by m and n values set by the machine clock (t mclk ) and cs4 to cs0 of iccr0 register. ? standard-mode : m and n can be set at the range : 0.9 mhz < t mclk (machine clock) < 10 mhz. setting of m and n limits the machin e clock that can be used below. (m, n) = (1, 8) : 0.9 mhz < t mclk 1 mhz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 mhz < t mclk 2 mhz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 mhz < t mclk 4 mhz (m, n) = (1, 98) : 0.9 mhz < t mclk 10 mhz ? fast-mode : m and n can be set at the range : 3.3 mhz < t mclk (machine clock) < 10 mhz. setting of m and n limits the machine clock that can be used below. (m, n) = (1, 8) : 3.3 mhz < t mclk 4 mhz (m, n) = (1, 22) , (5, 4) : 3.3 mhz < t mclk 8 mhz (m, n) = (6, 4) : 3.3 mhz < t mclk 10 mhz parameter sym- bol pin name condition value* 2 unit remarks min max data hold time t hd;dat scl0 sda0 r = 1.7 k ? , c = 50 pf* 1 0 ? ns at reception data setup time t su;dat scl0 sda0 t mclk ? 20 ? ns at reception sda scl (at wake-up function) t wakeup scl0 sda0 oscillation stabilization wait time + 2 t mclk ? 20 ? ns
mb95100am series ds07-12614-3e 59 (9) low voltage detection (avss = vss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol value unit remarks min typ max release voltage v dl+ 2.52 2.70 2.88 v at power-supply rise detection voltage v dl- 2.42 2.60 2.78 v at power-supply fall hysteresis width v hys 70 100 ? mv power-supply start voltage v off ?? 2.3 v power-supply end voltage v on 4.9 ?? v power-supply voltage change time (at power supply rise) t r 0.3 ?? s slope of power supply that reset release signal generates ? 3000 ? s slope of power supply that reset release signal generates within rating (v dl+ ) power-supply voltage change time (at power supply fall) t f 300 ?? s slope of power supply that reset detection signal generates ? 300 ? s slope of power supply that reset detection signal generates within rating (v dl- ) reset release delay time t d1 ?? 400 s reset detection delay time t d2 ?? 30 s current consumption i lvd ? 38 50 a current consumption for low voltage detection circuit only v hys t d2 t d1 t r t f v cc v cc v on v off v dl+ v dl- internal reset signal time time
mb95100am series 60 ds07-12614-3e (10) clock supervisor clock (vcc = avcc = 5.0 v 10 % , avss = vss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol value unit remarks min typ max oscillation frequency f out 50 100 200 khz oscillation start time t wk ?? 10 s current consumption i csv ? 20 36 a current consumption of built-in cr oscillator, at oscillation of 100 khz
mb95100am series ds07-12614-3e 61 5. a/d converter (1) a/d converter electrical characteristics (avcc = vcc = 4.0 v to 5.5 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol value unit remarks min typ max resolution ? ?? 10 bit total error ? 3.0 ? + 3.0 lsb linearity error ? 2.5 ? + 2.5 lsb differential linear error ? 1.9 ? + 1.9 lsb zero transition voltage v ot avss ? 1.5 lsb avss + 0.5 lsb avss + 2.5 lsb v full-scale transition voltage v fst avr ? 3.5 lsb avr ? 1.5 lsb avr + 0.5 lsb v compare time ? 0.9 ? 16500 s4.5 v avcc 5.5 v 1.8 ? 16500 s4.0 v avcc < 4.5 v sampling time ? 0.6 ?? s 4.5 v avcc 5.5 v, at external impedance < 5.4 k ? 1.2 ?? s 4.0 v avcc < 4.5 v, at external impedance < 2.4 k ? analog input current i ain ? 0.3 ? + 0.3 a analog input voltage v ain avss ? avr v reference voltage ? avss + 4.0 ? avcc v avr pin reference voltage supply current i r ? 600 900 a avr pin, during a/d operation i rh ?? 5 a avr pin, at stop mode
mb95100am series 62 ds07-12614-3e (2) notes on using a/d converter ? about the external impedance of analog input and its sampling time a/d converter with sample and hold circuit. if the ex ternal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample an d hold capacitor is insufficient, adversely affecting a/ d conversion precision. therefore, to satisfy the a/d conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. also, if the sampling time cannot be suff icient, connect a capacitor of about 0.1 f to the analog input pin. ? about errors as |avr ? av ss | becomes smaller, values of relative errors grow larger. r c analog input note : the values are reference values. ? analog input equivalent circuit rc 4.5 v avcc 5.5 v 2.0 k ? (max) 16 pf (max) 4.0 v avcc < 4.5 v 8.2 k ? (max) 16 pf (max) comparator during sampling : on 0 2 46 8 10 12 14 0 10 20 30 40 50 60 70 80 90 100 av cc 4.5 v av cc 4.0 v 01234 0 2 4 6 8 10 12 14 16 18 20 av cc 4.5 v av cc 4.0 v (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 20 k ? ) minimum sampling time [ s] external impedance [k ? ] minimum sampling time [ s] external impedance [k ? ] ? the relationship between external impedance and minimum sampling time
mb95100am series ds07-12614-3e 63 (3) definition of a/d converter terms resolution the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, an alog voltage can be divided into 2 10 = 1024. linearity error (unit : lsb) the deviation between the value along a straight lin e connecting the zero transition point (?00 0000 0000? ?00 0000 0001?) of a device and the fu ll-scale transition point (?11 1111 1111? ?11 1111 1110?) compared with the actual conversion values obtained. differential linear error (unit : lsb) deviation of input voltage, which is required for ch anging output code by 1 lsb, from an ideal value. total error (unit: lsb) difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. (continued) v fst 1.5 lsb 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 1 lsb 0.5 lsb v ot av ss avr av ss v nt avr {1 lsb ( n ? 1 ) + 0.5 lsb} 1 lsb = avr ? avss 1024 (v) total error of digital output n v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb ideal i/o characteristics total error digital output analog input analog input digital output [lsb] actual conversion characteristic actual conversion characteristic ideal characteristics n : a/d converter digital output value v nt : a voltage at which digital output transits from (n ? 1) to n. =
mb95100am series 64 ds07-12614-3e (continued) av ss avr av ss avr av ss avr v nt av ss avr 001 h 002 h 003 h 004 h 3fc h 3fd h 3fe h 3ff h 001 h 002 h 003 h 004 h 3fd h 3fe h 3ff h n - 2 h n - 1 h n h n + 1 h {1 lsb n + v ot } v nt v ( n + 1 ) t full-scale transition error digital output actual conversion characteristic actual conversion characteristic ideal characteristics analog input v fst (measurement value) zero transition error digital output actual conversion characteristic actual conversion characteristic analog input v ot (measurement value) ? 1 differential linear error in digital output n v (n + 1) t ? v nt 1 lsb linearity error in digital output n v nt ? {1 lsb n + v ot } 1 lsb linearity error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics differential linear error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics v fst (measurement value) v ot (measurement value) n : a/d converter digital output value v nt : a voltage at which digital output transits from (n ? 1) to n. v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = avr ? 1.5 lsb [v] ideal characteristics = =
mb95100am series ds07-12614-3e 65 6. flash memory program/erase characteristics *1 : t a = + 25 c, v cc = 5.0 v, 10000 cycles *2 : t a = + 85 c, v cc = 4.5 v, 10000 cycles *3 : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . parameter value unit remarks min typ max sector erase time (4 kbytes sector) ? 0.2* 1 0.5* 2 s excludes 00 h programming prior erasure. sector erase time (16 kbytes sector) ? 0.5* 1 7.5* 2 s excludes 00 h programming prior erasure. byte programming time ? 32 3,600 s excludes system-level overhead. erase/program cycle 10000 ?? cycle power supply voltage at erase/ program 4.5 ? 5.5 v flash memory data retention time 20* 3 ?? year average t a = + 85 c
mb95100am series 66 ds07-12614-3e mask option * : refer to table below about clock mode select, low volta ge detection reset, clock supervisor select and reset output. no. part number mb95108am mb95f104ams mb95f104ans mb95f104ajs mb95f106ams mb95f106ans mb95f106ajs mb95f108ams mb95f108ans mb95f108ajs mb95f104amw mb95f104anw mb95f104ajw mb95f106amw mb95f106anw mb95f106ajw mb95f108amw mb95f108anw mb95f108ajw mb95fv100d-103 specifying procedure specify when ordering mask setting disabled setting disabled setting disabled 1 clock mode select ? single-system clock mode ? dual-system clock mode selectable single-system clock mode dual-system clock mode changing by the switch on mcu board 2 low voltage detection reset* ? with low voltage detection reset ? without low voltage detection reset specify when ordering mask specified by part number specified by part number changing by the switch on mcu board 3 clock supervisor* ? with clock supervisor ? without clock supervisor specify when ordering mask specified by part number specified by part number changing by the switch on mcu board 4 reset output* ? with reset output ? without reset output specify when ordering mask specified by part number specified by part number mcu board switch set as following ; ? with supervisor : without reset output ? without supervisor : with reset output 5 oscillation stabilization wait time fixed to oscillation stabilization wait time of (2 14 -2) /f ch fixed to oscillation stabilization wait time of (2 14 -2) /f ch fixed to oscillation stabilization wait time of (2 14 -2) /f ch fixed to oscillation stabilization wait time of (2 14 -2) /f ch
mb95100am series ds07-12614-3e 67 part number clock mode select low voltage detection reset clock supervisor reset output mb95108am single-system no no yes yes no yes yes yes no dual-system no no yes yes no yes yes yes no mb95f104ams single-system no no yes mb95f104ans yes no yes mb95f104ajs yes yes no mb95f106ams no no yes mb95f106ans yes no yes mb95f106ajs yes yes no mb95f108ams no no yes mb95f108ans yes no yes mb95f108ajs yes yes no mb95f104amw dual-system no no yes mb95f104anw yes no yes mb95f104ajw yes yes no mb95f106amw no no yes mb95f106anw yes no yes mb95f106ajw yes yes no mb95f108amw no no yes mb95f108anw yes no yes mb95f108ajw yes yes no mb95fv100d-103 single-system no no yes yes no yes yes yes no dual-system no no yes yes no yes yes yes no
mb95100am series 68 ds07-12614-3e ordering information part number package mb95108ampfv mb95f104amspfv/f104anspfv/f104ajspfv mb95f104amwpfv/f104anwpfv/f104ajwpfv mb95f106amspfv/f106anspfv/f106ajspfv mb95f106amwpfv/f106anwpfv/f106ajwpfv mb95f108amspfv/f108anspfv/f108ajspfv mb95f108amwpfv/f108anwpfv/f108ajwpfv 64-pin plastic lqfp (fpt-64p-m03) MB95108AMPFM mb95f104amspfm/f104anspfm/f104ajspfm mb95f104amwpfm/f104anwpfm/f104ajwpfm mb95f106amspfm/f106anspfm/f106ajspfm mb95f106amwpfm/f106anwpfm/f106ajwpfm mb95f108amspfm/f108anspfm/f108ajspfm mb95f108amwpfm/f108anwpfm/f108ajwpfm 64-pin plastic lqfp (fpt-64p-m09) mb2146-303 (mb95fv100d-103pbt) mcu board ( ) 224-pin plastic pfbga (bga-224p-m08)
mb95100am series ds07-12614-3e 69 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ (continued) 64-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 10.0 10.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0. 3 2g code (reference) p-lfqfp64-10 10-0.50 64-pin pl as tic lqfp (fpt-64p-m0 3 ) (fpt-64p-m0 3 ) lead no. det a il s of "a" p a rt 0.25(.010) ( s t a nd off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.00 8 ) 0.500.20 1.50 +0.20 ?0.10 +.00 8 ?.004 .059 0 ~ 8 "a" 0.0 8 (.00 3 ) (.006.002) 0.1450.055 0.0 8 (.00 3 ) m (.00 8 .002) 0.200.05 0.50(.020) 12.000.20(.472.00 8 ) s q 10.000.10(. 3 94.004) s q index 49 64 33 4 8 17 3 2 16 1 200 3 -200 8 fujit s u microelectronic s limited f64009 s -c-5-9 c (mo u nting height) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb95100am series 70 ds07-12614-3e (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ 64-pin pl as tic lqfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 12 12 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max code (reference) p-lqfp64-12 12-0.65 64-pin pl as tic lqfp (fpt-64p-m09) (fpt-64p-m09) c 200 3 -200 8 fujit s u microelectronic s limited f6401 8s -c- 3 -6 0.65(.026) 0.10(.004) 116 17 3 2 49 64 33 4 8 12.000.10(.472.004) s q 14.000.20(.551.00 8 ) s q index 0. 3 20.05 (.01 3 .002) m 0.1 3 (.005) 0.1450.055 (.0057.0022) "a" .059 ?.004 +.00 8 ?0.10 +0.20 1.50 0~ 8 0.25(.010) (mo u nting height) 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0.100.10 (.004.004) det a il s of "a" p a rt ( s t a nd off) 0.10(.004) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb95100am series ds07-12614-3e 71 main changes in this edition the vertical lines marked in the left side of the p age show the changes. page section change results 10 pin description changed the f unction of pin number 11. (the pin is shared with 16-bit relord timer ch.0 output the pin is shared with 16-bit relord timer ch.0 input) changed the function of pin number 12. (the pin is shared with 16-bit relord timer ch.0 input the pin is shared with 16-bit relord timer ch.0 output)
mb95100am series fujitsu microelectronics limited shinjuku dai-ichi seimei bldg ., 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3347 fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu microelectronics asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fmal.fujitsu.com/ fujitsu microelectronics shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fa x : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of f unction and application circuit examples, in this document are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu microelectronics device; fujitsu microelectronics does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incor porating the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu microelectronics assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of f unction and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microelectronics warrant non-i nfringement of any third-party's intellectual property right o r other right by using such information. fujitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers th at, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to d eath, personal injury, severe physical damage or other loss (i.e., nuclear reaction con trol in nuclear facility, aircraft flight control, air tr affic control, mass transport control, me dical life support system, missile launch con trol in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any third party for any claims or damages arisi ng in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety design measures into your facility and equi pment such as redundancy, fire protection, and prevention of ov er-current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

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